As microelectronic devices have been continuously provided with a larger integration scale, planarization processes used for manufacturing such microelectronic devices have become more and more important. As a part of attempts to obtain very large scale integrated microelectronic devices, multiple interconnection technique and multilayer stacking technique have generally been used for semiconductor wafers. However, non-planarization occurring after carrying out one of the above techniques causes many problems. Therefore, planarization processes are applied to various steps in a microelectronic device manufacturing process, so as to minimize irregularity on wafer surfaces.
One of these planarization techniques is CMP (chemical mechanical polishing). During the process of CMP, a wafer surface is pressed against a polishing pad that rotates relative to the surface, and an abrasive and a chemical reagent known as CMP slurry is introduced into the polishing pad during the polishing process, so that planarization of a wafer surface is accomplished by way of chemical and physical actions.
One example, to which the CMP process is applied, is shallow trench isolation (STI). In the STI technique, relatively shallow trenches are formed, and such trenches are used in forming field regions for separating active regions on wafer surfaces.
A general STI process is shown in FIG. 1. As shown in FIG. 1, a pad silicon oxide (SiO2) layer 101 and a silicon nitride (Si3N4) layer 102 are formed successively on a semiconductor wafer. Next, a photoresist pattern is formed on the Si3N4 layer 102. Then, the Si3N4 layer 102, the pad silicon oxide layer 101 and the semiconductor wafer 100 are partially etched by using the photoresist pattern as a mask, so that a plurality of trenches 103 is formed.
Further, in order to form field regions, an insulating silicon oxide layer 104 is deposited by way of LPCVD (low pressure chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition) or HDPCVD (high density plasma chemical vapor deposition) technique, so that the trenches 103 are filled with the layer 104 and the surface of the Si3N4 layer 102 is covered with the layer 104. Subsequently, the insulating silicon oxide layer 104 is polished until the Si3N4 layer 102 is exposed. Additionally, the Si3N4 layer 102 placed between two adjacent active regions, as well as the pad silicon oxide layer 101 is removed by etching. Finally, a gate silicon oxide layer 105 is formed on the surface of the semiconductor wafer.
Herein, during the progress of the CMP process for removing the insulating silicon oxide layer 104, the insulating silicon oxide layer 104 and the Si3N4 layer 102 show different removal rates due to their different chemical and physical properties.
The ratio of the removal rate of the insulating silicon oxide layer to that of the silicon nitride layer is referred to as the selectivity of CMP slurry. As the selectivity of CMP slurry decreases, the amount of the Si3N4 layer removed by the slurry increases. It is preferable that the Si3N4 layer is not removed. In other words, preferably the selectivity of the insulating silicon oxide layer to the Si3N4 layer is infinite. However, conventional CMP slurry has a low polishing selectivity of the insulating silicon oxide layer to the Si3N4 layer, which is about 4:1. Hence, the Si3N4 layer is polished to a degree exceeding the acceptable range in a practical CMP process. As a result, the Si3N4 layer pattern may be removed non-uniformly depending on locations in a wafer during a CMP process. Therefore, the Si3N4 layer has a variable thickness over the whole wafer. Particularly, this is a serious problem in the case of a semiconductor wafer that has a highly dense pattern simultaneously with a sparse pattern. Due to the above-mentioned problem, a final structure having field regions has a level difference between active regions and field regions, resulting in reduction of the margin of subsequent steps for manufacturing a semiconductor device, and degradation of the quality of a transistor and a device. Briefly, conventional CMP processes are problematic in that a Si3N4 layer pattern with a uniform thickness cannot be obtained even after removing the oxide layer via a CMP process.
In addition to such problems occurring in local planarization, the conventional technology has many problems in global planarization of a wafer. When the global cross section of a wafer polished according to the conventional technology is analyzed, it can be seen that the central portion of the wafer is polished more than the edge portion, so that the wafer shows a U-shaped or W-shaped cross section and has high within-wafer non-uniformity. It is known that the reason for such polishing characteristics is that the distribution of mechanical pressure against a wafer and a polishing pad is non-uniform, so that the distribution of abrasive slurry or abrasive particles during polishing is non-uniform, and thus the polishing rate of the central portion of the wafer is relatively increased.
Due to this high within-wafer non-uniformity, in actual semiconductor processes, the process margin of a silicon nitride layer is increased to stably secure the end time point of polishing. For example, it is possible to use a method of forming an initial silicon nitride layer thicker than the thickness difference of a polished silicon nitride layer between the central portion and edge portion of the wafer. However, this method has a problem of causing process inefficiency.
Prior techniques relating to the preparation of this STI CMP slurry will now be described.
The following patent documents relating to a method for preparing a high-selectivity cerium oxide slurry, invented in Hitachi Chemical Co., Ltd., Japan, disclose additives for achieving dispersion stability and high selectivity in cerium oxide slurry compositions: Japanese Patent Laid-Open Publication No. 1998-106988; Japanese Patent Laid-Open Publication No. 1998-154672; Japanese Patent Laid-Open Publication No. 1998-27041; Japanese Patent Publication Nos. 2000-109794 and 2000-109815 (Apr. 18, 2000); Japanese Patent Laid-Open Publication Nos. 2001-37951, 2001-35820 and 2001-319900; Korean Patent Laid-Open Publication Nos. 2001-0108048 and 2002-0015697; U.S. Pat. No. 6,211,118B1 (Apr. 24, 2001) and U.S. Pat. No. 6,420,269B2 (Jul. 16, 2002). However, such techniques according to the prior art are problematic in that their application ranges are too broad and are not clearly defined, and merely provide basic information about polishing rates and selectivity ratios. Therefore, such techniques are not practically applicable. In addition, these patent documents do not disclose technical contents and effects about the global planarization of wafers.
In addition to the above, domestic semiconductor and slurry fabricating companies have developed an additive for increasing the polishing selectivity of cerium oxide slurry, the additive comprising a linear polymer alone or in combination with a low-molecular weight material. Such additives are disclosed in Korean Laid-Open Patent Nos. 2003-0039999, 2004-0057653, 2004-0013299, 2004-0098671, 2004-0095118 and 2005-0004051. However, these patent documents disclose only increasing polishing rate and polishing selectivity and do not disclose technical contents and effects about global planarization characteristics.
Meanwhile, as prior techniques for improving global planarization characteristics, a method of adding an additive comprising an organic polymer material, for example, is known. However, this method has a problem in that it increases the viscosity of slurry, because a significant amount of the additive should be added in order to reduce within-wafer non-uniformity to the desired level.